R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 2026

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Rev. 2.00 May 22, 2009 Page 1956 of 1982
REJ09B0256-0200
Item
14.3.7 DMA Channel
Control Registers
(CHCR0 to CHCR5)
Page
585
Added
Revision (See Manual for Details)
Bit
1
Bit Name Descriptions
TE
Transfer End Flag
Shows that DMA transfer ends. The TE bit is set to
1 when data transfer ends when TCR becomes to
0.
The TE bit is not set to 1 in the following cases.
•
•
To clear the TE bit, the TE bit should be written to 0
after reading 1. However, when the TE bit is not
cleared, always write 1 to this bit.
Even if the DE bit is set to 1 while this bit is set to 1,
transfer is not enabled.
0: During the DMA transfer or DMA transfer has
[Clearing condition]
Writing 0 after TE = 1 read
1: DMA transfer ends by the specified count (TCR =
been interrupted
0)
DMA transfer ends due to an NMI interrupt or
DMA address error before TCR is cleared to 0.
DMA transfer is ended by clearing the DE bit
and DME bit in DMAOR.