R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1035

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

CAM evaluation can be referenced during frame processing in reception (for details on the CAM
function, refer to section 23.4.5, CAM Function).
When 1 is written to the RR bit in EDRRR while the RE bit in ECMR is set to 1, the E-DMAC
reads the descriptor following the previously used descriptor from the receive descriptor list (or
the descriptor indicated by RDLAR at the initial startup) then enters the receive wait state. If 32
bytes or more of data or the last byte of the receive frame is stored in the receive FIFO, the E-
DMAC transfers receive FIFO data to the receive buffer specified by RD2 according to the receive
descriptor with the RACT bit set to 1 (valid).
If the data length of a received frame is longer than the buffer length specified by RD1, the E-
DMAC performs a write-back operation to the descriptor (set RFP to 10 or 00) when the buffer is
full, then reads the next descriptor. The E-DMAC then continues to transfer data to the receive
buffer specified by the new RD2.
When the following conditions are satisfied, a write-back operation is performed for the descriptor
(RFP = 11 or 01), 11 is written to the FR bits in EESR, and an interrupt is issued to the CPU.
• The receive buffer has been full during DMA transfer.
• DMA transfer to the receive buffer of the last byte of the receive frame has been completed.
Legend
SFD: Start frame delimiter
Note: The error frame also transmits data to the buffer.
lllegal carrrier
Reception
detection
halted
Reset
RE set
Figure 23.10 E-MAC Receiver State Transitions
RE reset
ldle
notification*
station destination address
Promiscuous and other
Error
detection
Premble
Recevice error
Start of frame
decection
reception
detection
Error
RX-DV negation
Section 23 Gigabit Ethernet Controller (GETHER)
Receive error
detection
Rev. 2.00 May 22, 2009 Page 965 of 1982
Destination address
Wait for SFD
reception
reception
reception
reception
Data
CRC
reception
Own destination address
or broadcast
or broadcast
or promiscuous
SFD
REJ09B0256-0200