R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1382

IC SUPERH MPU ROMLESS 499BGA

R5S77631Y266BGV

Manufacturer Part Number
R5S77631Y266BGV
Description
IC SUPERH MPU ROMLESS 499BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R5S77631Y266BGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
266MHz
Connectivity
Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
107
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
499-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5S77631Y266BGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 31 Multimedia Card Interface (MMCIF)
31.3.12 Interrupt Control Registers 0 and 1 (INTCR0, INTCR1)
The INTCR registers enable or disable the INTSTR0 and INTSTR1 flags and control the interrupt
outputs.
• INTCR0
Rev. 2.00 May 22, 2009 Page 1312 of 1982
REJ09B0256-0200
Bit
7
6
5
4
3
2
1
Bit Name
FEIE
FFIE
DRPIE
DTIE
CRPIE
CMDIE
DBSYIE
Initial value:
Initial
Value
0
0
0
0
0
0
0
R/W:
Bit:
FEIE
R/W
7
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FFIE
R/W
6
0
Description
FIFO Empty Flag Enable
0: Disables FIFO empty flag setting.
1. Enables FIFO empty flag setting.
FIFO Full Flag Enable
0: Disables FIFO full flag setting.
1: Enables FIFO full flag setting.
Data Response End Flag Enable
0: Disables data response end flag setting.
1: Enables data response end flag setting.
Data Transfer End Flag Enable
0: Disables data transfer end flag setting.
1: Enables data transfer end flag setting.
Command Response End Flag Enable
0: Disables command response end flag setting.
1: Enables command response end flag setting.
Command Output End Flag Enable
0: Disables command output end flag setting.
1: Enables command output end flag setting.
Data Busy End Flag Enable
0: Disables data busy end flag setting.
1: Enables data busy end flag setting.
DRPIE
R/W
5
0
DTIE
R/W
4
0
CRPIE CMDIE DBSYIE BTIE
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0

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