R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 658

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 14 Direct Memory Access Controller (DMAC)
Note:
Rev. 2.00 May 22, 2009 Page 588 of 1982
REJ09B0256-0200
Bit
1
0
*
Bit Name
NMIF
DME
Writing 0 is possible to clear the flag.
Initial
Value
0
0
R/W
R/(W)* NMI Flag
R/W
Descriptions
Indicates that an NMI interrupt occurred. If this bit is
set, DMA transfer is disabled even if the DE bit in
CHCR and the DME bit in DMAOR are set to 1.
When the NMI is input, the DMA transfer in progress
can be done in at least one transfer unit. When the
DMAC is not in operational, the NMIF bit is set to 1
even if the NMI interrupt was input.
0: No NMI interrupt
[Clearing condition]
Writing 0 after NMIF = 1 is read.
However, when the NMIF bit is not cleared, always
write 1 to this bit.
1: NMI interrupt occurs
Note: DMA transfer is stopped when an NMI interrupt is
DMA Master Enable
Enables or disables DMA transfers on all channels. If
the DME bit and the DE bit in CHCR are set to 1,
transfer is enabled. In this time, all of the bits TE in
CHCR, NMIF, and AE in DMAOR must be 0. If this bit
is cleared during transfer, transfers in all channels are
terminated.
0: Disables DMA transfers on all channels
1: Enables DMA transfers on all channels
Note: To abort the DMA transfer when the on-chip
peripheral module request mode is set for any of
the channels specified by DMAOR (channel 0 to
5), clear the DE bit to 0 while the DMA transfer
request from the corresponding peripheral
module is cleared.
input. After returning from the NMI interrupt
routine, set all channels again, and then start the
DMA transfer.