R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 829

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

21.3.4
The setting of bits CMR1 and CMR0 in CMCSR selects the sending of a request for a DMA
transfer or for an internal interrupt to the CPU at a compare match.
A DMA transfer request has different specifications according to the CMT channel as described
below.
1. For channels 0 and 1, a single DMA transfer request is output at a compare match.
2. For channels 2 to 4, a DMA transfer request continues until the amount of data transferred has
To clear the interrupt request, the CMF bit should be set to 0. Set the CMF bit to 0 in the handling
routine for the CMT interrupt.
21.3.5
The CMF bit in CMCSR is set to 1 by the compare match signal generated when CMCOR and
CMCNT match. The compare match signal is generated upon the final state of the match (timing
at which the CMCNT value is updated to H'0000). Consequently, after CMCOR and CMCNT
match, a compare match signal will not be generated until a CMCNT counter clock is input.
Figure 21.4 shows the set timing of the CMF bit.
reached the value set in the DMAC, and the output of the request then automatically stops.
DMA Transfer Requests and Internal Interrupt Requests to CPU
Compare Match Flag Set Timing (All Channels)
Counter clock
CMCNT
CMCOR
Compare match signal
and interrupt signal
Peripheral operating
clock (Pck0)
Figure 21.4 CMF Set Timing
N
N
N + 1
clock
Rev. 2.00 May 22, 2009 Page 759 of 1982
Section 21 Compare Match Timer (CMT)
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