R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1238
R5S77631Y266BGV
Manufacturer Part Number
R5S77631Y266BGV
Description
IC SUPERH MPU ROMLESS 499BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R5S77631Y266BGV.pdf
(2056 pages)
Specifications of R5S77631Y266BGV
Core Processor
SH-4A
Core Size
32-Bit
Speed
266MHz
Connectivity
Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
107
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
499-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5S77631Y266BGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
In clocked synchronous serial communication, data on the communication line is output from one
fall of the synchronization clock to the next fall. Data is guaranteed to be accurate at the start of
the synchronization clock.
In serial communication, each character is output starting with the LSB and ending with the MSB.
After the MSB is output, the communication line remains in the state of the last data.
In clocked synchronous mode, the SCIF receives data in synchronization with the rise of the
synchronization clock.
(1)
A fixed 8-bit data format is used. No parity bit can be added.
(2)
Either an internal clock generated by the on-chip baud rate generator or an external
synchronization clock input at the SCIF_SCK pin can be selected as the SCIF's serial clock,
according to the settings of the C/A bit in SCSMR and the CKE1 and CKE0 bits in SCSCR. For
details of SCIF clock source selection, see table 28.7.
When the SCIF is operated on an internal clock, the synchronization clock is output from the
SCIF_SCK pin. Eight synchronization clock pulses are output in the transfer of one character, and
when no transfer is performed the clock is fixed high. When an internal clock is selected in a
receive operation only, as long as the RE bit in SCSCR is set to 1, clock pulses are output until the
number of receive data bytes in the receive FIFO data register reaches the receive trigger number.
(3)
Before transmitting and receiving data, it is necessary to clear the TE and RE bits in SCSCR to 0,
then initialize the SCIF as described below.
When changing the operating mode or transfer format, etc., the TE and RE bits must be cleared to
0 before making the change using the following procedure. When the TE bit is cleared to 0,
SCTSR is initialized. Note that clearing the RE bit to 0 does not initialize the RDF, PER, FER, or
ORER flag state or change the contents of SCFRDR.
Rev. 2.00 May 22, 2009 Page 1168 of 1982
REJ09B0256-0200
Data Transfer Format
Clock
SCIF Initialization (Clocked Synchronous Mode):
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