R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1024

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 23 Gigabit Ethernet Controller (GETHER)
(3)
(a)
Each transmit descriptor specifies one transmit buffer. The E-DMAC transfers a transmit frame
stored in a transmit buffer specified by a transmit descriptor to the transmit FIFO. Multiple
transmit frames stored in transmit buffers specified by multiple descriptors can be connected into
one transmit frame and transferred to the transmit FIFO.
Figure 23.5 shows the relationship between the transmit descriptors and transmit buffers.
(b) Reception
Each receive descriptor specifies one receive buffer. The E-DMAC receives a receive frame from
the receive FIFO and stores it in a receive buffer specified by a receive descriptor. If the receive
frame size exceeds the receive buffer size, the remaining data of the receive frame can be stored in
Rev. 2.00 May 22, 2009 Page 954 of 1982
REJ09B0256-0200
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 1
Tfansmit descriptor ring
(in memory)
Transmit descriptor 1
Transmit descriptor 2
Transmit descriptor 3
Transmit descriptor 4
Transmit descriptor 5
Transmit descriptor 6
Transmit descriptor 7
Transmit descriptor 8
(Transmit frame C)
(Transmit frame C)
(Transmit frame D)
(Transmit frame A)
(Transmit frame B)
(Transmit frame B)
(Transmit frame B)
(Transmit frame E)
1
1
0
0
1
0
1
1
Descriptor and Transmit/Receive Buffer
Transmission
1
0
0
1
0
1
1
1
Figure 23.5 Relationship between Transmit Descriptor and Transmit Buffer
TACT
TDL
TFP[1:0]
Transimit buffer 7
Tfansmit buffer
(in memory)
Transimit buffer 2
Transmit buffer 1
Transmit buffer 4
Transmit buffer 5
Transmit buffer 6
Transmit buffer 8
Transmit buffer 3
4 bytes
Transmit frame data
(Transmit data transferred by DMA transfer from
memory to transmit FIFO is configured as a frame
in the MAC and output to the GMII/MII/RMII.)
Transmit buffer 2 to 4 are connected to be one frame
(transmit frame B) and output to the GMII/MII/RMII.
Transmit frame C
Transmit buffer 5 and 6 are connented to be one frame.
(transmit frame C) arnd output to the GMII/MII/RMII.
Transmit frame D
Transmit frame E
Transmit buffer 1
Transmit buffer 4
Transmit buffer 6
Transmit buffer 7
Transmit buffer 8
Transmit frame A
Transmit frame B
Transmit buffer 3
Transmit buffer 5
Transimit buffer 2