R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 754

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 18 Power-Down Mode
18.7.2
The sequence when the system power supply is turned off is shown below.
Figure 18.2 shows the sequence of entering the self-refresh mode and turning off the system
power supply.
1. Confirm that all transactions of the DDRIF caused by on-chip peripheral modules are
2. Issue the all bank precharge command (PREALL) with bits SMS2 to SMS0 in SCR by
3. Specify the DRE and RMODE bits in the MIM register of the DDRIF to put the SDRAM into
4. The SELFS bit in MIM is set to 1.
5. Drive the M_BKPRST pin from high to low.
6. Turn off the system power supply (1.2 V and 3.3 V).
Rev. 2.00 May 22, 2009 Page 684 of 1982
REJ09B0256-0200
PRESET
DDRIF reset
VDD
(1.2 V, 3.3 V)
M_CKE
M_BKPRST
completed.
software. Activated banks will be closed. After that, issue the auto-refresh command (REFA)
with bits SMS2 to SMS0 in SCR to perform CBR refresh on all rows.
the self-refresh mode. At this time, keep the DCE bit set to 1. The DDRIF automatically issues
a self-refresh command and drives the M_CKE signal low. After that, the DDR-SDRAM will
automatically enter the power-down mode.
The M_CKE output will be unstable immediately after the system power supply is turned off.
Therefore, before turning off the system power supply, use the M_BKPRST signal, which is a
signal outside the LSI, to keep the M_CKE signal input of the DDR-SDRAM low until the
power-on reset is canceled (figure 18.1).
DDR-SDRAM Backup Sequence when Turning Off System Power Supply
Transition to self-refresh
mode completed
Figure 18.1 DDR-SDRAM Interface Operation when
Turning System Power Supply On/Off
System power
turned off
supply
System power
turned on
supply
Power-on
canceled
reset
Delay time of
LSI internal reset
by SMS bits in SCR
M_CKE asserted