R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 246
R5S77631Y266BGV
Manufacturer Part Number
R5S77631Y266BGV
Description
IC SUPERH MPU ROMLESS 499BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R5S77631Y266BGV.pdf
(2056 pages)
Specifications of R5S77631Y266BGV
Core Processor
SH-4A
Core Size
32-Bit
Speed
266MHz
Connectivity
Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
107
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
499-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
R5S77631Y266BGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 6 Memory Management Unit (MMU)
6.6.4
The UTLB data array is allocated to addresses H'F700 0000 to H'F70F FFFF in the P4 area. A
data array access requires a 32-bit address field specification (when reading or writing) and a 32-
bit data field specification (when writing). Information for selecting the entry to be accessed is
specified in the address field, and PPN, V, SZ, PR, C, D, SH, and WT to be written to data array
are specified in the data field.
In the address field, bits [31:20] have the value H'F70 indicating UTLB data array and the entry is
specified by bits [13:8].
In the data field, bits [28:10] indicate PPN, bit [8] indicates V, bits [7] and [4] indicate SZ, bits
[6:5] indicate PR, bit [3] indicates C, bit [2] indicates D, bit [1] indicates SH, and bit [0] indicates
WT.
The following two kinds of operation can be used on UTLB data array:
1. UTLB data array read
2. UTLB data array write
Rev. 2.00 May 22, 2009 Page 176 of 1982
REJ09B0256-0200
PPN, V, SZ, PR, C, D, SH, and WT are read into the data field from the UTLB entry
corresponding to the entry set in the address field.
PPN, V, SZ, PR, C, D, SH, and WT specified in the data field are written to the UTLB entry
corresponding to the entry set in the address field.
UTLB Data Array
Address field
Data field
Figure 6.14 Memory-Mapped UTLB Address Array
31
31
1 1 1 1 0 1 1 0 0 0 0 0
VPN:
D:
V:
E:
*:
Virtual page number
Validity bit
Entry
Dirty bit
Don't care
20
VPN
19
* * * * *
ASID:
A:
:
Address space identifier
Association bit
Reserved bits (write value should be 0
and read value is undefined )
14 13
*
E
10 9 8 7
D
V
8 7
A
* * * * *
ASID
2 1
0 0
0
0
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