R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 999

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

23.3.81 Receive Descriptor Fetch Address Register (RDFAR)
RDFAR stores the descriptor start address that is required when the E-DMAC fetches descriptor
information from the receive descriptor. Which receive descriptor information is used for
processing by the E-DMAC can be recognized by monitoring addresses displayed in this register.
The address from which the E-DMAC is actually fetching a descriptor may be different from the
value read from this register. In the initial setting, set the address of the receive descriptor at which
receive processing is to be started.
Bit
0
Bit
31 to 0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Bit Name
RNC
Bit Name
RDFA[31:0]
R/W
R/W
31
15
0
0
R/W
R/W
30
14
0
0
R/W
R/W
29
13
0
0
Initial
Value
0
Initial
Value
All 0
R/W
R/W
28
12
0
0
R/W
R/W
27
11
0
0
R/W
R/W
R/W
R/W
R/W
R/W
26
10
0
0
Description
Receive Enable Control
Sets whether to continue frame reception.
0: Upon completion of reception of one frame, the E-
1: Upon completion of reception of one frame, the E-
Description
Receive Descriptor Fetch Address
Writing to these bits during the reception is prohibited.
R/W
R/W
25
DMAC writes the receive status to the descriptor and
clears the RR bit in EDRRR to 0.
DMAC writes (writes back) the receive status to the
descriptor. In addition, the E-DMAC reads the next
descriptor and prepares for reception of the next
frame.
0
9
0
R/W
R/W
RDFA[31:16]
RDFA[15:0]
24
0
8
0
Section 23 Gigabit Ethernet Controller (GETHER)
R/W
R/W
23
0
7
0
Rev. 2.00 May 22, 2009 Page 929 of 1982
R/W
R/W
22
0
6
0
R/W
R/W
21
0
5
0
R/W
R/W
20
0
4
0
R/W
R/W
19
0
3
0
REJ09B0256-0200
R/W
R/W
18
0
2
0
R/W
17
0
1
0
R/W
R/W
16
0
0
0