R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 879

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

23.3.1
ARSTR resets all blocks (E-MAC, TSU, and E-DMAC) in the GETHER. By writing 1 to the
ARST bit in this register, a software reset is issued to all blocks of the GETHER (for 256 cycles of
external bus clock Bck). The ARST bit is always read as 0. While a software reset is issued,
register access to all blocks of the GETHER is prohibited.
Bit
31 to 1
0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Software Reset Register (ARSTR)
Bit Name

ARST
31
15


R
R
0
0
30
14


R
R
0
0
29
13


R
R
0
0
Initial
Value
All 0
0
28
12


R
R
0
0
27
11
R/W
R
R/W


R
R
0
0
26
10


R
R
0
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Software Reset
When 1 is written to this bit, a software reset is issued
to all blocks of the GETHER (for 256 cycles of external
bus clock Bck). Writing 0 does not affect this bit. This
bit is always read as 0. While a software reset is
issued, register access to all blocks of the GETHER is
prohibited. The following registers are not initialized by
a software reset.
TSU_ADRH0 to TSU_ADRH31, TSU_ADRL0 to
TSU_ADRL31, TXNLCR0, TXNLCR1, TXALCR0,
TXALCR1, RXNLCR0, RXNLCR1, RXALCR0,
RXALCR1, FWNLCR0, FWNLCR1, FWALCR0,
FWALCR1
When relay operations from the E-MAC-1 to E-MAC-0
or from the E-MAC-0 to E-MAC-1 are enabled, a reset
must be issued using this bit. A software reset issued
by the SWRT and SWRR bits in EDMR does not reset
the transfer switching unit (TSU) performing data
transfer between the E-MAC-1 and E-MAC-0.
25

R

R
0
9
0
24

R

R
0
8
0
Section 23 Gigabit Ethernet Controller (GETHER)
23


R
R
0
7
0
Rev. 2.00 May 22, 2009 Page 809 of 1982
22


R
R
0
6
0
21


R
R
0
5
0
20

R

R
0
4
0
19


R
R
0
3
0
REJ09B0256-0200
18


R
R
0
2
0
17


R
0
1
0
ARST
R/W
16

R
0
0
0