R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 417

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

11.4.4
The CSn wait control register (CSnWCR) is a 32-bit readable/writable register that specifies the
number of wait cycles to be inserted, the pitch of data access for burst memory accesses, and the
number of cycles to be inserted for the address setup time to the read/write strobe assertion or for
the data hold time from the write strobe negation.
This allows direct connection of even low-speed memories without an external circuit.
CSnBCR is initialized to H'7777 770F by a power-on reset or a manual reset.
Initial value:
Initial value:
Bit
31
30 to 28 ADS
R/W:
R/W:
Bit:
Bit:
CSn Wait Control Register (CSnWCR)
Bit Name

31
−
15
−
R
R
0
0
R/W
R/W
30
14
1
1
WTS
ADS
R/W
R/W
Initial
Value
0
111
29
13
1
1
R/W
R/W
28
12
1
1
R/W
R
R/W
R/W
27
−
11
−
R
0
0
R/W
R/W
26
10
1
1
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
Address Setup Cycle
Specify the number of cycles to be inserted to ensure
the address setup time to the CSn assertion. (Available
only when the SRAM interface, byte control SRAM
interface, or burst ROM interface is selected.)
000: No cycle inserted
001: 1 cycle inserted
010: 2 cycles inserted
011: 3 cycles inserted
100: 4 cycles inserted
101: 5 cycles inserted
110: 6 cycles inserted
111: 7 cycles inserted
WTH
ADH
R/W
R/W
25
1
9
1
R/W
R/W
24
1
8
1
23
−
−
R
R
Section 11 Local Bus State Controller (LBSC)
0
7
0
Rev. 2.00 May 22, 2009 Page 347 of 1982
R/W
R/W
22
1
6
0
RDS
BSH
R/W
R/W
21
1
5
0
R/W
R/W
20
1
4
0
R/W
19
−
R
0
3
1
REJ09B0256-0200
R/W
R/W
18
1
2
1
IW[3:0]
RDH
R/W
R/W
17
1
1
1
R/W
R/W
16
1
0
1