R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 574

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 13 PCI Controller (PCIC)
(10) PCI Arbiter Interrupt Register (PCIAINT)
In host bus bridge mode, this register records source of an interrupt. When multiple interrupts
occur, only the first source is registered. When an interrupt is disabled, source is registered in
corresponding bit (set to 1) in this register, however, no interrupt occurs.
Rev. 2.00 May 22, 2009 Page 504 of 1982
REJ09B0256-0200
Initial value:
Initial value:
Bit
31 to 14 
13
PCI R/W:
PCI R/W:
SH R/W:
SH R/W:
Bit:
Bit:
Bit Name
MBI
31
15
—
—
R
R
R
R
0
0
30
14
—
—
R
R
R
R
0
0
R/WC
MBI
Initial
Value
All 0
0
29
13
—
R
R
R
0
0
R/WC
TOI
28
12
TB
—
R
R
R
0
0
R/W
SH: R
PCI: R
SH: R/WC
PCI: R
R/WC
TOI
MB
27
—
11
R
R
R
0
0
26
10
—
—
R
R
R
R
0
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Master-Broken Interrupt
An interrupt is detected when the PCIFRAME signal is
not asserted within 16 clock cycles, although the
PCIC gave a master the bus.
0: Master-broken interrupt does not occur
[Clear condition]
Write 1 to this bit (write clear).
1: Master-broken interrupt occurs
[Set condition]
When a master-broken interrupt occurs.
25
—
—
R
R
R
R
0
9
0
24
—
—
R
R
R
R
0
8
0
23
—
—
R
R
R
R
0
7
0
22
—
—
R
R
R
R
0
6
0
21
—
—
R
R
R
R
0
5
0
20
—
—
R
R
R
R
0
4
0
R/WC
TAI
19
—
R
R
R
0
3
0
R/WC
MAI
18
—
R
R
R
0
2
0
R/WC
PEI
RD
17
—
R
R
R
0
1
0
R/WC
WD
PEI
16
—
R
R
R
0
0
0