R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1608

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 36 USB Function Controller (USBF)
36.3.27 Trigger Register (TRG)
TRG generates one-shot triggers FIFO for each endpoint of EP0s, EP0i, EP0o, EP1, EP2, and
EP3. The packet enable trigger for the IN FIFO register and read complete trigger for the OUT
FIFO register are triggers to be given.
Rev. 2.00 May 22, 2009 Page 1538 of 1982
REJ09B0256-0200
Bit
31 to 8 
7
6
5
4
3
2
1
0
Initial value:
Initial value:
R/W:
R/W:
Bit: 31
Bit: 15
Bit Name

EP3 PKTE
EP1 RDFN
EP2 PKTE

EP0s RDFN
EP0o RDFN
EP0i PKTE
—
—
—
—
R
R
30
—
14
—
—
—
R
R
29
—
13
—
—
—
R
R
Initial Value R/W Description
Undefined
0
0
0
0
0
0
0
0
28
—
12
—
—
—
R
R
27
—
11
—
—
—
R
R
26
—
10
—
—
—
R
R
R
W
W
W
W
W
W
W
W
25
—
—
—
—
R
R
9
Reserved
The write value should always be 0.
EP3 Packet Enable
EP1 Read Complete
EP2 Packet Enable
Reserved
The write value should always be 0.
EP0s Read Complete
EP0o Read Complete
EP0i Packet Enable
Reserved
These bits are always read as undefined value.
Write value should always be 0.
24
—
—
—
—
R
R
8
23
—
—
—
W
R
7
0
PKTE
EP3
22
—
—
W
R
6
0
RDFN
EP1
21
—
—
W
R
5
0
PKTE
EP2
20
—
—
W
R
4
0
19
—
—
—
W
R
3
0
RDFN
EP0s
18
—
—
W
R
2
0
RDFN
EP0o
17
—
—
W
R
1
0
PKTE
EP0i
—
16
—
W
R
0
0