R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1732

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 38 A/D Converter
38.3.2
ADCSR is a 16-bit readable/writable register that selects the mode and controls the A/D converter.
ADCSR is initialized to H'0080 by a reset and in standby mode.
Rev. 2.00 May 22, 2009 Page 1662 of 1982
REJ09B0256-0200
Initial value:
Bit
15
14
Note: * Only 0 can be written to clear the flag.
R/W:
Bit:
Bit Name
ADIE
ADF
R/(W)*
A/D Control/Status Registers (ADCSR)
ADF
15
0
ADIE
R/W
14
0
Initial Value R/W
0
0
ADST
R/W
13
0
12
—
R
0
11
—
R
0
R/(W)* A/D End Flag
R/W
10
—
R
0
Description
Indicates the end of A/D conversion.
[Clearing conditions]
(1) Cleared by reading ADF while ADF = 1, then
[Setting conditions]
Single mode: A/D conversion ends
Multi mode: A/D conversion has cycled through the
selected channels (A/D conversion cycles through the
selected channels)
Scan mode: A/D conversion has cycled through the
selected channels (A/D conversion is continuously
repeated for the selected channels)
Note: When clearing the ADST bit to 0 to stop A/D
A/D Interrupt Enable
Enables or disables the interrupt (ADI) requested at
the end of A/D conversion. Set the ADIE bit while A/D
conversion is not being made.
0: A/D end interrupt request (ADI) is disabled
1: A/D end interrupt request (ADI) is enabled
—
R
9
0
writing 0 to ADF
conversion in scan mode or in multi mode (ADF
= 0), after clearing the ADST bit to 0, read the
ADST bit in ADCSR and confirm that it is 0.
Then, after at least the time for A/D conversion
on one channel has elapsed, set the ADST bit to
1 again. Note that the A/D conversion time
differs according to the A/D conversion clock
division ratio.
—
R
8
0
R/W
7
0
CKS[1:0]
R/W
6
1
R/W
5
0
MDS[1:0]
R/W
4
0
—
R
3
0
R/W
2
0
CH[2:0]
R/W
1
0
R/W
0
0