R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 575

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
12
11
10 to 4
Bit Name
TBTOI
MBTOI

Initial
Value
0
0
All 0
R/W
SH: R/WC
PCI: R
SH: R/WC
PCI: R
SH: R
PCI: R
Description
Target Bus Time-Out Interrupt
An interrupt is detected when the TRDY or STOP
signal is not asserted within 16 clock cycles on the
first data transfer.
An interrupt is detected when the TRDY or STOP
signal is not asserted within eight clock cycles during
the data transfer subsequent to the 2nd.
0: Target bus time-out interrupt does not occur
[Clear condition]
Write 1 to this bit (write clear).
1: Target bus time-out interrupt occurs
[Set condition]
When a target bus time-out interrupt occurs.
Master Bus Time-Out Interrupt
An interrupt is detected when the IRDY signal is not
asserted within 8 clock cycles.
0: Master bus time-out interrupt does not occur
[Clear condition]
Write 1 to this bit (write clear).
1: Master bus time-out interrupt occurs
[Set condition]
When a master bus time-out interrupt occurs.
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00 May 22, 2009 Page 505 of 1982
Section 13 PCI Controller (PCIC)
REJ09B0256-0200