R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 339

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

9.3.15
INT2A01 (mask state is not affected) is a 32-bit read-only register that indicates interrupt source
modules. Even if interrupt masking is set in the interrupt mask register, INT2A01 indicates a
source module in a corresponding bit (the corresponding interrupt is not generated). If source
indication is not necessary depending on the state of the interrupt mask register, use INT2A11.
Initial value:
Initial value:
Bit
12
11 to 9 —
8
7
6
5
4
3
2
1
0
R/W:
R/W:
Bit:
Bit:
Bit Name
CMT
DMAC
H-UDI
—
WDT
SCIF1
SCIF0
RTC
TMU1
TMU0
Interrupt Source Register 01 (Mask State is not affected) (INT2A01)
PCC
−
31
15
R
R
0
0
Note: * This bit is reserved in the R5S77631A.
30
14
−
R
−
R
0
0
Initial
Value
0
All 0
0
0
0
0
0
0
0
0
0
29
13
−
−
R
R
0
0
ADC
28
12
−
R
R
0
0
R/W
R
R
R
R
R
R
R
R
R
R
R
TPU
27
11
−
R
R
0
0
SIM SIOF2 SIOF1 LCDC
Function
Indicates CMT interrupt source
write value should always be 0.
Indicates DMAC interrupt source
Indicates H-UDI interrupt source
This bit is always read as 0. The
write value should always be 0.
Indicates WDT interrupt source
Indicates SCIF1 interrupt source
Indicates SCIF0 interrupt source
Indicates RTC interrupt source
Indicates TMU1 interrupt source
Indicates TMU0 interrupt source
This bit is always read as 0. The
26
10
−
R
R
0
0
SCIF2 USBF
25
R
R
0
9
0
24
R
R
0
8
0
23
−
R
R
0
7
0
Rev. 2.00 May 22, 2009 Page 269 of 1982
22
−
−
R
R
0
6
0
Section 9 Interrupt Controller (INTC)
STIF1 STIF0
IIC1
21
R
R
0
5
0
IIC0
20
R
R
0
4
0
Description
Indicates interrupt
sources for each
peripheral module
(INT2A0 is not
affected by the state
of the interrupt mask
register).
0: No interrupts
1: Interrupts are
Note: Reading the
SSI3
generated
19
−
R
R
0
3
0
INTEVT code
notified to the
CPU directly
can identify
interrupt
sources. In this
case, reading
INT2A0 is not
necessary.
REJ09B0256-0200
SSI2
18
−
R
R
0
2
0
USBH
SSI1
17
R
R
0
1
0
GETH
SECU
RITY*
ER
16
R
R
0
0
0