R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1101

IC SUPERH MPU ROMLESS 499BGA

R5S77631Y266BGV

Manufacturer Part Number
R5S77631Y266BGV
Description
IC SUPERH MPU ROMLESS 499BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R5S77631Y266BGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
266MHz
Connectivity
Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
107
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
499-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5S77631Y266BGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
26.3.1
Bit
7 to 4
3
2
1
Slave Control Register (ICSCR)
Bit Name
SDBS
SIE
GCAE
Initial value:
Initial Value
All 0
0
0
0
R/W:
Bit:
R
7
0
R
6
0
R/W
R
R/W
R/W
R/W
R
5
0
Description
Reserved
The write value should always be 0.
Slave Data Buffer Select
This bit is used to select the data buffer. The
double-buffer mode and single-buffer mode are
available.
When this bit is set to 0, the double-buffer mode
is selected. During a reception, as long as both
buffers are full and the SDR flag has not been
cleared, SCL is held low. When the SDR flag is
cleared, the low level state of SCL is released.
When this bit is set to 1, the single-buffer mode is
selected. SCL will be held low from the timing
when the receive data register acquires the data
packet until the SDR flag is cleared.
0: Double-buffer mode
1: Single-buffer mode
Slave Interface Enable
This bit must be set for the slave operation. If this
bit is low, the slave interface is reset.
This bit is cleared by setting the MIE bit to 1.
General Call Acknowledgement Enable
When a master requires a slave to issue an
acknowledgement, this bit must be set to 1
R
4
0
SDBS
R/W
3
0
Rev. 2.00 May 22, 2009 Page 1031 of 1982
R/W
SIE
2
0
GCAE
R/W
1
0
Section 26 I
R/W
FNA
0
0
2
C Bus Interface (IIC)
REJ09B0256-0200

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