R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 284

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 7 Caches
7.7.4
Determination of an exception in a write to an SQ or transfer to external memory (PREF
instruction) is performed as follows according to whether the MMU is enabled or disabled. If an
exception occurs during a write to an SQ, the SQ contents before the write are retained. If an
exception occurs in a data transfer from an SQ to external memory, the transfer to external
memory will be aborted.
• When MMU is enabled (AT = 1 in MMUCR)
• When MMU is disabled (AT = 0 in MMUCR)
7.7.5
In privileged mode in this LSI, reading the contents of the SQs may be performed by means of a
load instruction for addresses H'FF00 1000 to H'FF00 103C in the P4 area. Only longword access
is possible.
[31:6]
[5]
[4:2]
[1:0]
Rev. 2.00 May 22, 2009 Page 214 of 1982
REJ09B0256-0200
Physical address bits [4:0] are always fixed at 0 since burst transfer starts at a 32-byte
boundary.
Operation is in accordance with the address translation information recorded in the UTLB, and
the SQMD bit in MMUCR. Write type exception judgment is performed for writes to the SQs,
and read type exception judgment for transfer from the SQs to external memory (using a PREF
instruction). As a result, a TLB miss exception or protection violation exception is generated
as required. However, if SQ access is enabled in privileged mode only by the SQMD bit in
MMUCR, an address error will occur even if address translation is successful in user mode.
Operation is in accordance with the SQMD bit in MMUCR.
0: Privileged/user mode access possible
1: Privileged mode access possible
If the SQ area is accessed in user mode when the SQMD bit in MMUCR is set to 1, an address
error will occur.
Determination of SQ Access Exception
Reading from SQ
: H'FF00 1000
: 0/1
: LW specification
: 00
Store queue specification
0: SQ0 specification
1: SQ1 specification
Specifies longword position in SQ0/SQ1
Fixed at 0