R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1013

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
31
30
Bit
Name
TACT
TDLE
Initial
Value
0
0
R/W
R/W
R/W
Description
Transmit Descriptor Valid/Invalid
Indicates whether the corresponding descriptor is valid or
invalid. To make this bit valid, store transmit data in a
transmit buffer (user-specified transmit data storage
destination) beforehand, then write 1 to this bit. The E-
DMAC clears this bit to 0 after data transfer.
0: Indicates that this transmit descriptor is invalid
1: Indicates that this transmit descriptor is valid
Transmit Descriptor List End
Indicates whether the corresponding descriptor is the last
descriptor of the descriptor row (descriptor list).
0: Not last descriptor
1: Last descriptor
written, or (in case the user writes 1 to this bit) that this
bit is cleared to 0 because the E-DMAC data transfer
processing is completed.
descriptor, the E-DMAC clears the TR bit in EDTRR to 0,
and halts transfer operation related to transmission by
the E-DMAC.
Indicates the initial setting state, the state after 0 is
If this state is recognized when the E-DMAC reads a
After transfer of the corresponding descriptor, the E-
After the user writes 1 to this bit, this bit indicates that
data is not transferred yet or data is being transferred.
When there is a descriptor row (descriptor list) consisting
of multiple continuous descriptors, the E-DMAC can
continue operation when this bit of the next descriptor is
valid.
After transfer of the corresponding descriptor, the E-
DMAC reads the next one in the list of continuous
descriptors.
DMAC reads the descriptor placed at the address
indicated by TDLAR.
Section 23 Gigabit Ethernet Controller (GETHER)
Rev. 2.00 May 22, 2009 Page 943 of 1982
REJ09B0256-0200