R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 35

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

37.4 Operation ......................................................................................................................... 1625
37.5 Clock and LCD Data Signal Examples............................................................................ 1643
37.6 Usage Notes ..................................................................................................................... 1655
Section 38 A/D Converter................................................................................1657
38.1 Features............................................................................................................................ 1657
38.2 Input Pins ......................................................................................................................... 1659
38.3 Register Descriptions ....................................................................................................... 1660
38.4 Operation ......................................................................................................................... 1665
37.3.7 LCDC Line Address Offset Register for Display Data Fetch (LDLAOR) ......... 1604
37.3.8 LCDC Palette Control Register (LDPALCR)..................................................... 1605
37.3.9 Palette Data Registers 00 to FF (LDPR00 to LDPRFF) ..................................... 1606
37.3.10 LCDC Horizontal Character Number Register (LDHCNR) ............................... 1607
37.3.11 LCDC Horizontal Sync Signal Register (LDHSYNR) ....................................... 1608
37.3.12 LCDC Vertical Display Line Number Register (LDVDLNR) ........................... 1609
37.3.13 LCDC Vertical Total Line Number Register (LDVTLNR)................................ 1610
37.3.14 LCDC Vertical Sync Signal Register (LDVSYNR) ........................................... 1611
37.3.15 LCDC AC Modulation Signal Toggle Line Number Register (LDACLNR) ..... 1612
37.3.16 LCDC Interrupt Control Register (LDINTR) ..................................................... 1613
37.3.17 LCDC Power Management Mode Register (LDPMMR) ................................... 1616
37.3.18 LCDC Power-Supply Sequence Period Register (LDPSPR) .............................. 1618
37.3.19 LCDC Control Register (LDCNTR)................................................................... 1620
37.3.20 LCDC User Specified Interrupt Control Register (LDUINTR).......................... 1621
37.3.21 LCDC User Specified Interrupt Line Number Register (LDUINTLNR) ........... 1623
37.3.22 LCDC Memory Access Interval Number Register (LDLIRNR) ........................ 1624
37.4.1 LCD Module Sizes which can be Displayed in this LCDC ................................ 1625
37.4.2 Limits on the Resolution of Rotated Displays, Burst Length, and Connected
37.4.3 Color Palette Specification ................................................................................. 1630
37.4.4 Data Format ........................................................................................................ 1631
37.4.5 Setting the Display Resolution............................................................................ 1635
37.4.6 Power-Supply Control Sequence ........................................................................ 1635
37.4.7 Operation for Hardware Rotation ....................................................................... 1640
37.6.1 Procedure for Halting Access to Display Data Storage VRAM
37.6.2 Notes on Using NMI Interrupt............................................................................ 1655
38.3.1 A/D Data Registers A to D (ADDRA to ADDRD) ............................................ 1660
38.3.2 A/D Control/Status Registers (ADCSR)............................................................. 1662
38.4.1 Single Mode (MDS1 = 0, MDS0 = 0)................................................................. 1665
38.4.2 Multi Mode (MDS[1:0] = 10) ............................................................................. 1666
Memory (SDRAM)............................................................................................. 1627
(DDR-SDRAM in Area 3) .................................................................................. 1655
Rev. 2.00 May 22, 2009 Page xxxiii of lxviii