R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 28

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

28.4 Operation ......................................................................................................................... 1153
28.5 Infrared Data Communication Interface .......................................................................... 1181
28.6 Baud Rate Generator for External Clock (BRG) ............................................................. 1183
Section 29 Serial I/O with FIFO (SIOF) ......................................................... 1187
29.1 Features............................................................................................................................ 1187
29.2 Input/Output Pins............................................................................................................. 1189
29.3 Register Descriptions....................................................................................................... 1190
29.4 Operation ......................................................................................................................... 1219
Rev. 2.00 May 22, 2009 Page xxvi of lxviii
28.3.8 Bit Rate Register (SCBRR) ................................................................................ 1143
28.3.9 FIFO Control Register (SCFCR) ........................................................................ 1144
28.3.10 FIFO Data Count Register (SCFDR).................................................................. 1146
28.3.11 Serial Port Register (SCSPTR) ........................................................................... 1147
28.3.12 Line Status Register (SCLSR) ............................................................................ 1149
28.3.13 BRG Frequency Division Register (BRGDL2) .................................................. 1150
28.3.14 BRG Clock Select Register (BRGCKS2) ........................................................... 1151
28.3.15 IrDA Serial Mode Register (SCSMRIR) ............................................................ 1152
28.4.1 Overview ............................................................................................................ 1153
28.4.2 Operation in Asynchronous Mode ...................................................................... 1157
28.4.3 Operation in Clocked Synchronous Mode .......................................................... 1167
28.4.4 SCIF Interrupt Sources and the DMAC.............................................................. 1176
28.4.5 Usage Notes ........................................................................................................ 1178
28.5.1 Infrared Data Communication Format................................................................ 1181
28.5.2 Operation of Infrared Data Communication Interface ........................................ 1182
28.6.1 BRG Block Diagram........................................................................................... 1183
28.6.2 Restrictions on the BRG ..................................................................................... 1184
29.3.1 Mode Register (SIMDR) .................................................................................... 1194
29.3.2 Clock Select Register (SISCR) ........................................................................... 1196
29.3.3 Control Register (SICTR)................................................................................... 1198
29.3.4 Transmit Data Register (SITDR) ........................................................................ 1201
29.3.5 Receive Data Register (SIRDR) ......................................................................... 1202
29.3.6 Transmit Control Data Register (SITCR) ........................................................... 1203
29.3.7 Receive Control Data Register (SIRCR) ............................................................ 1204
29.3.8 Status Register (SISTR)...................................................................................... 1205
29.3.9 Interrupt Enable Register (SIIER) ...................................................................... 1211
29.3.10 FIFO Control Register (SIFCTR) ....................................................................... 1213
29.3.11 Transmit Data Assign Register (SITDAR) ......................................................... 1215
29.3.12 Receive Data Assign Register (SIRDAR) .......................................................... 1216
29.3.13 Control Data Assign Register (SICDAR) ........................................................... 1217
29.4.1 Serial Clocks....................................................................................................... 1219