R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 23

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

23.3.10 PHY_INT Polarity Register (PIPR)...................................................................... 824
23.3.11 Transmit Retry Over Counter Register (TROCR) ................................................ 825
23.3.12 Delayed Collision Detect Counter Register (CDCR)............................................ 826
23.3.13 Lost Carrier Counter Register (LCCR)................................................................. 827
23.3.14 CRC Error Frame Receive Counter Register (CEFCR)........................................ 828
23.3.15 Frame Receive Error Counter Register (FRECR)................................................. 829
23.3.16 Too-Short Frame Receive Counter Register (TSFRCR)....................................... 830
23.3.17 Too-Long Frame Receive Counter Register (TLFRCR)....................................... 831
23.3.18 Residual-Bit Frame Receive Counter Register (RFCR) ....................................... 832
23.3.19 Carrier Extension Loss Counter Register (CERCR) ............................................. 833
23.3.20 Carrier Extension Error Counter Register (CEECR) ............................................ 834
23.3.21 Multicast Address Frame Receive Counter Register (MAFCR)........................... 835
23.3.22 Automatic PAUSE Frame Register (APR) ........................................................... 836
23.3.23 Manual PAUSE Frame Register (MPR) ............................................................... 837
23.3.24 Automatic PAUSE Frame Retransmit Count Register (TPAUSER) .................... 838
23.3.25 PAUSE Frame Transmit Counter Register (PFTCR) ........................................... 839
23.3.26 PAUSE Frame Receive Counter Register (PFRCR)............................................. 840
23.3.27 GETHER Mode Register (GECMR) .................................................................... 841
23.3.28 Burst Cycle Count Upper-Limit Register (BCULR)............................................. 842
23.3.29 TSU Counter Reset Register (TSU_CTRST) ....................................................... 843
23.3.30 Relay Enable Register (Port 0 to 1) (TSU_FWEN0) ............................................ 844
23.3.31 Relay Enable Register (Port 1 to 0) (TSU_FWEN1) ............................................ 845
23.3.32 Relay FIFO Size Select Register (TSU_FCM) ..................................................... 846
23.3.33 Relay FIFO Overflow Alert Set Register (Port 0) (TSU_BSYSL0) ..................... 847
23.3.34 Relay FIFO Overflow Alert Set Register (Port 1) (TSU_BSYSL1) ..................... 849
23.3.35 Transmit/Relay Priority Control Mode Register (Port 0) (TSU_PRISL0)............ 851
23.3.36 Transmit/Relay Priority Control Mode Register (Port 1) (TSU_PRISL1)............ 853
23.3.37 Receive/Relay Function Set Register (Port 0 to 1) (TSU_FWSL0)...................... 855
23.3.38 Receive/Relay Function Set Register (Port 1 to 0) (TSU_FWSL1)...................... 857
23.3.39 Relay Function Set Register (Common) (TSU_FWSLC)..................................... 859
23.3.40 Qtag Addition/Deletion Set Register (Port 0 to 1) (TSU_QTAG0) ...................... 861
23.3.41 Qtag Addition/Deletion Set Register (Port 1 to 0) (TSU_QTAG1) ...................... 862
23.3.42 Relay Status Register (TSU_FWSR) .................................................................... 863
23.3.43 Relay Status Interrupt Mask Register (TSU_FWINMK)...................................... 866
23.3.44 Added Qtag Value Set Register (Port 0 to 1) (TSU_ADQT0).............................. 869
23.3.45 Added Qtag Value Set Register (Port 1 to 0) (TSU_ADQT1).............................. 870
23.3.46 VLANtag Set Register (Port 0) (TSU_VTAG0)................................................... 871
23.3.47 VLANtag Set Register (Port 1) (TSU_VTAG1)................................................... 872
23.3.48 CAM Entry Table Busy Register (TSU_ADSBSY) ............................................. 873
23.3.49 CAM Entry Table Enable Register (TSU_TEN) .................................................. 874
Rev. 2.00 May 22, 2009 Page xxi of lxviii