R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 197

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

(10) Slot Illegal Instruction Exception
• Sources:
• Transition address: VBR + H'000 0100
• Transition operations:
Slot_illegal_instruction_exception()
{
}
 Decoding of an undefined instruction in a delay slot
 Decoding of an instruction that modifies PC in a delay slot
 Decoding in user mode of a privileged instruction in a delay slot
 Decoding of a PC-relative MOV instruction or MOVA instruction in a delay slot
The PC contents for the preceding delayed branch instruction are saved in SPC. The SR and
R15 contents when this exception occurred are saved in SSR and SGR.
Exception code H'1A0 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a
branch is made to PC = VBR + H'0100. Operation is not guaranteed if an undefined code other
than H'FFFD is decoded.
SPC = PC - 2;
SSR = SR;
SGR = R15;
EXPEVT = H'0000 01A0;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
PC = VBR + H'0000 0100;
Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S
Undefined instruction: H'FFFD
Instructions that modify PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF,
BT/S, BF/S, TRAPA, LDC Rm,SR, LDC.L @Rm+,SR, ICBI, PREFI
Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP, but excluding LDC/STC
instructions that access GBR
Rev. 2.00 May 22, 2009 Page 127 of 1982
Section 5 Exception Handling
REJ09B0256-0200