R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 524

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 13 PCI Controller (PCIC)
13.2
Table 13.1 shows the pin configuration of the PCIC.
Table 13.1 Input/Output Pins
Rev. 2.00 May 22, 2009 Page 454 of 1982
REJ09B0256-0200
Pin Name
AD31 to AD0
CBE3 to CBE0 C/BE[3:0]
PAR
PCICLK
PCIFRAME
TRDY
IRDY
STOP
LOCK
Input/Output Pins
PCI standard
signal name
AD[31:0]
PAR
CLK
FRAME
TRDY
IRDY
STOP
LOCK
I/O
I/O
(TRI)
I/O
(TRI)
I/O
(TRI)
Input
I/O
(STRI)
I/O
(STRI)
I/O
(STRI)
I/O
(STRI)
I/O
(STRI)
Description
PCI Address/Data Bus
Address and data buses are multiplexed. Each bus
transaction consists of an address phase followed by
one or more data phases.
PCI Command/Byte Enable
Bus command and byte enables are multiplexed.
These signals indicate the type of transaction during
the address phase and the byte enables during the
data phases.
PCI Parity
Generates/checks even parity across AD[31:0] and
CBE[3:0].
PCI Clock
Provides timing for all transactions on the PCI bus.
PCI Frame
Current initiator drives this signal, which indicates the
start and duration or end of a transaction.
PCI Target Ready
Selected target drives this signal, which indicates the
target is ready to execute a transaction. During a write,
this signal indicates that the target is ready to accept
data. During a read, this signal indicates that valid data
is present on the AD [31:0] lines.
PCI Initiator Ready
The current bus master drives this signal. During a
write, this signal indicates that valid data is present on
the AD [31:0] lines. During a read, this signal indicates
that the master is ready to accept data.
PCI Stop
Selected target drives this signal to stop the current
transaction.
PCI Lock