R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1239

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Figure 28.13 shows a sample SCIF initialization flowchart.
in SCSCR (leaving TE, RE, TIE,
Set RTRG1-0 and TTRG1-0 bits
Set TE and RE bits in SCSCR
and ER flags in SCFSR, and
in SCFCR, and clear TFCL
and RIE bits cleared to 0)
Set CKE1 and CKE0 bits
Set TFCL and RFCL bits
Set data transfer format
After reading BRK, DR,
in SCFCR to 1 to clear
1-bit interval elapsed?
to 1, and set TIE, RIE,
ORER flag in SCLSR,
write 0 to clear them
Clear TE and RE bits
Set value in SCBRR
and RFCL bits to 0
Start of initialization
End of initialization
the FIFO buffer
in SCSCR to 0
and REIE bits
in SCSMR
Yes
Wait
Figure 28.13 Sample SCIF Initialization Flowchart
Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
No
[1]
[2]
[3]
[4]
[5]
[1]
[2]
[3]
[4]
[5]
Leave the TE and RE bits cleared to 0 until the
initialization almost ends.
Set the CKE1 and CKE0 bits.
Set the data transfer/receive format in SCSMR.
Write a value corresponding to the bit rate into SCBRR.
This is not necessary if an external clock is used.
Wait at least one bit interval after this write before moving
to the next step.
Set the TE or RE bit in SCSCR to 1. Also set the TIE, RIE,
and REIE bits to enable the SCIF_TXD, SCIF_RXD,
and SCIF_CLK pins to be used. When transmitting,
the SCIF_TXD pin will go to the mark state. When
receiving in clocked synchronous mode with the
synchronization clock output (clock master) selected,
a clock starts to be output from the SCIFn_SCK pin
at this point.
Rev. 2.00 May 22, 2009 Page 1169 of 1982
REJ09B0256-0200