R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1376

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 31 Multimedia Card Interface (MMCIF)
31.3.8
OPCR aborts command operation, and suspends or continues data transfer.
Rev. 2.00 May 22, 2009 Page 1306 of 1982
REJ09B0256-0200
Bit
7
6
5
Operation Control Register (OPCR)
Bit Name
CMDOFF
—
RD_CONTI 0
Initial value:
Initial
Value
0
0
R/W:
Bit:
CMD
R/W
OFF
7
0
R/W
R/W
R
R/W
—
R
6
0
Description
Command Off
Aborts all command operations (MMCIF command
sequence) when 1 is written to it after a command is
transmitted. This bit is then cleared by hardware.
Write enabled period: From command transmission
completion to command sequence end
Write 0: Operation is not affected.
Write 1: Command sequence is forcibly aborted.
Reserved
This bit is always read as 0. The write value should
always be 0.
Read Continue
This bit is cleared by hardware when 1 is written and
the MMCIF resumes data read.
Read data reception is resumed while the sequence
has been halted by FIFO full or termination of block
reading in multiblock read.
Write enabled period: While read data reception is
halted
Write 0: Operation is not affected.
Write 1: Resumes read data reception.
CONTI DATEN
R/W
RD_
5
0
R/W
4
0
—
R
3
0
—
R
2
0
—
R
1
0
—
R
0
0