R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1681

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

37.3.14 LCDC Vertical Sync Signal Register (LDVSYNR)
LDVSYNR specifies the vertical (scan direction and vertical direction) sync signal timing of the
LCD module.
Initial value:
Bit
15 to 12 VSYNW[3:0]
11
10 to 0
R/W:
Bit:
Bit Name

VSYNP[10:0] 00111011111 R/W Vertical Sync Signal Output Position
R/W
15
0
R/W
VSYNW[3:0]
14
0
R/W
13
0
Initial Value
0000
0
R/W
12
0
11

R
0
R/W
10
0
R/W Description
R/W Vertical Sync Signal Width
R
R/W
9
0
Set the width of the vertical sync signals (FLM and
Vsync) (unit: line).
Specify to the value of (the vertical sync signal
width) -1.
Example: For a vertical sync signal width of 1 line.
Reserved
This bit is always read as 0. The write value should
always be 0.
Set the output position of the vertical sync signals
(FLM and Vsync) (unit: line).
Specify to the value of (the number of vertical sync
signal output position) -2.
DSTN should be set to an odd number value. It is
handled as (setting value+1)/2.
Example: For an 480-line LCD module and a vertical
retrace period of 0 lines (in other words, VTLN=479
and the vertical sync signal is active for the first line):
•
•
R/W
Single display
VSYNP = [(1-1)+VTLN]mod(VTLN+1)
Dual displays
VSYNP = [(1-1)×2+VTLN]mod(VTLN+1)
8
1
R/W
7
1
VSYNW = (1-1) = 0 = H'0
= [(1-1)+479]mod(479+1)
= 479mod480 = 479 =H'1DF
= [(1-1)×2+479]mod(479+1)
= 479mod480 = 479 =H'1DF
Rev. 2.00 May 22, 2009 Page 1611 of 1982
R/W
6
1
VSYNP[10:0]
R/W
Section 37 LCD Controller (LCDC)
5
0
R/W
4
1
R/W
3
1
REJ09B0256-0200
R/W
2
1
R/W
1
1
R/W
0
1