R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1084

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 25 Stream Interface (STIF)
25.3.6
STIPNR sets the number of packets of the stream data to be transmitted or received.
Rev. 2.00 May 22, 2009 Page 1014 of 1982
REJ09B0256-0200
Initial value:
Initial value:
Bit
31 to 21 
20 to 0
R/W:
R/W:
Bit:
Bit:
Transmit/Receive Packet Count Registers 0, 1 (STIPNR0, STIPNR1)
Bit Name
PN[20:0]
R/W
−
31
15
R
0
0
R/W
30
−
14
R
0
0
Initial
Value
All 0
All 0
R/W
29
−
13
R
0
0
R/W
28
12
−
R
0
0
R/W
R/W
R
R/W
−
27
11
R
0
0
R/W
26
−
10
R
0
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Number of Transmit/Receive Packets
These bits set the number of packets for transmission
or reception. An interrupt occurs when the number of
packets actually transmitted or received has reached
the value set in these bits. An interrupt does not occur
when 0 is set in these bits.
R/W
25
−
R
0
9
0
R/W
24
−
R
PN[15:0]
0
8
0
R/W
23
−
R
0
7
0
R/W
22
−
R
6
0
0
R/W
21
−
R
0
5
0
R/W
R/W
20
0
4
0
R/W
R/W
19
0
3
0
PN[20:16]
R/W
R/W
18
0
2
0
R/W
17
0
1
0
R/W
R/W
16
0
0
0