R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 707

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

The functions of the blocks in the CPG are as follows.
(1)
PLL circuit 1 multiples the frequency of the crystal oscillator or the clock input from the EXTAL
pin by the ratio of ×16. The multiplication ratio is selected by the combination of mode control
pins MD0, MD1, and MD2.
(2)
PLL circuit 2 aligns the phases of the bus clock (Bck) and the clock signal output from the
CLKOUT pin that is used by the external peripheral interface.
(3)
The crystal oscillator is a clock pulse generator used when a crystal resonator is connected to the
XTAL or EXTAL pin. The crystal oscillator can be enabled by the MD8 pin setting.
(4)
Divider 1 generates the CPU clock (Ick), SHwy clock (SHck), peripheral module clocks (Pck0,
Pck1), and bus clock (Bck). The division ratio is selected by the combination of mode control pins
MD0, MD1, and MD2.
(5)
The frequency control register is a read-only register that depends on the combination of mode
control pins MD0, MD1, and MD2.
(6)
PLL circuit 3 multiples the frequency of the SHwy clock (SHck) by the ratio of ×4.
(7)
Divider 2 generates the DDR-memory clocks (DDRck0, DDRck90, DDRck180, and DDRck270).
(8)
The PLL control register has control bits assigned for enabling or disabling the CLKOUT pin
output.
PLL Circuit 1
PLL Circuit 2
Crystal Oscillator
Divider 1
Frequency Control Register (FRQCR)
PLL Circuit 3
Divider 2
PLL Control Register (PLLCR)
Rev. 2.00 May 22, 2009 Page 637 of 1982
Section 16 Clock Pulse Generator (CPG)
REJ09B0256-0200