R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 985

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
20
19
18
17
Bit Name
TDE
TFUF
FR
RDE
0
Initial
Value
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
Transmit Descriptor Empty
Indicates that the transmit descriptor valid bit (TACT) of
a transmit descriptor read by the E-DMAC is not set if
the previous descriptor does not represent the end of a
frame in multi-buffer frame processing based on single-
frame/multi-descriptor operation. As a result, an
incomplete frame may be sent.
0: Transmit descriptor active bit TACT = 1 detected
1: Transmit descriptor active bit TACT = 0 detected
When transmit descriptor empty (TDE = 1) occurs,
execute a software reset and initiate transmission. In
this case, transmission starts from the address that is
stored in the transmit descriptor list start address
register (TDLAR).
Transmit FIFO Underflow
Indicates that an underflow has occurred in the transmit
FIFO during frame transmission. Incomplete data is
sent onto the line.
0: Underflow has not occurred
1: Underflow has occurred
Frame Reception
Indicates that a frame has been received and the
receive descriptor has been updated. This bit is set to 1
each time a frame is received.
0: Frame has not been received
1: Frame has been received
Receive Descriptor Empty
Indicates that the RACT bit of a receive descriptor read
by the E-DMAC for receive DMA operation is cleared to
0 (invalid).
When receive descriptor empty (RDE = 1) occurs,
reception can be resumed by setting the RACT bit
(cleared to 0) of the receive descriptor to 1 and then
writing 1 to the RR bit in EDRRR.
0: Receive descriptor active bit RACT = 1 detected
1: Receive descriptor active bit RACT = 0 detected
Section 23 Gigabit Ethernet Controller (GETHER)
Rev. 2.00 May 22, 2009 Page 915 of 1982
REJ09B0256-0200