R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1078

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 25 Stream Interface (STIF)
25.3.2
STICR enables or disables the STIF module and sets the packet interval for stream data
transmission.
Initial value:
Initial value:
Rev. 2.00 May 22, 2009 Page 1008 of 1982
REJ09B0256-0200
Bit
31 to 28 
27 to 16 ICYC[11:0] All 0
15
14 to 1
0
R/W:
R/W:
Bit:
Bit:
Control Registers 0, 1 (STICR0, STICR1)
Bit Name

EN
RST
RTS
R/W
−
31
15
R
0
0
30
−
14
−
R
R
0
0
Initial
Value
All 0
0
All 0
0
−
−
29
13
R
R
0
0
−
−
28
12
R
R
0
0
R/W
27
11
−
R
0
0
R/W
R
R/W
R/W
R
R/W
R/W
26
10
−
R
0
0
Description
These bits are always read as 0. The write value
should always be 0.
Number of Cycles between Transmit Packets
These bits set the fixed value when a fixed value is
used as the number of cycles between packets
during transmission. 1 to 4096 cycles of peripheral
clock 0 can be inserted as idle cycles between
packets.
Writing 1 to this bit resets the STIF module. This bit is
always read as 0.
These bits are always read as 0. The write value
should always be 0.
0: STIF module is disabled
1: STIF module is enabled
Reserved
STIF Module Reset
Reserved
STIF Module Enable
R/W
25
−
R
0
9
0
R/W
24
R
0
8
−
0
R/W
23
−
R
0
7
0
ICYC[11:0]
R/W
22
−
R
0
6
0
R/W
21
R
−
0
5
0
R/W
20
−
R
0
4
0
R/W
19
−
R
0
3
0
R/W
18
−
R
0
2
0
R/W
17
−
0
1
0
R/W
R/W
EN
16
0
0
0