R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1093

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

(2)
(a)
• Timing chart
• I/O selection for ST_CLK pin
• Active level setting for ST_START, ST_VALID, and ST_REQ pins
• Selection of ST_REQ pin usage
(b) Transmit Packet Length
The transmit packet length can be selected from 188 and 192 bytes.
Since the packet length is handled as 192 bytes in external memory, the first four bytes of a packet
are removed before transmission when the transmit packet length is set to 188 bytes. When the
transmit packet length is set to 192 bytes, external memory data is transmitted without changes.
Figure 25.5 shows the timing of the clock valid transmission interface.
For the ST_CLK pin, input of an external clock or output of an internally generated clock can
be selected by the CKSL bit in STIMDR (maximum frequency is 33 MHz).
The active levels of the ST_START, ST_VALID, and ST_REQ pins can be set by the STAT,
VLD, and REQ bits in STIMDR, respectively.
Whether or not to use the ST_REQ pin can be selected by the REQEN bit in STIMDR.
When usage of the ST_REQ pin is enabled, the ST_VALID pin is negated within four bytes
after assertion of the ST_REQ pin.
When usage of the ST_REQ pin is disabled, the ST_VALID pin is not negated until 188 or
192 bytes have been transferred.
Clock Valid Transmission
Clock Valid Transmission Interface
ST_CLK (input/output)
ST_START (output)
ST_VALID (output)
ST_REQ (input)
ST_D7 to ST_D0
(output)
Figure 25.5 Clock Valid Transmission Timing
Rev. 2.00 May 22, 2009 Page 1023 of 1982
Section 25 Stream Interface (STIF)
REJ09B0256-0200