R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1276

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 29 Serial I/O with FIFO (SIOF)
Rev. 2.00 May 22, 2009 Page 1206 of 1982
REJ09B0256-0200
Bit
12
11
10
Bit Name
TDREQ
—
RCRDY
Initial
Value
0
0
0
R/W
R
R
R
Description
Transmit Data Transfer Request
0: Indicates that the size of empty space in the transmit
1: Indicates that the size of empty space in the transmit
A transmit data transfer request is issued when the
empty space in the transmit FIFO exceeds the size
specified by the TFWM bit in SIFCTR.
When using transmit data transfer through the DMAC,
this bit is always cleared by one DMAC access. After
DMAC access, when conditions for setting this bit are
satisfied, the SIOF again indicates 1 for this bit.
•
•
•
Reserved
This bit is always read as 0. The write value should
always be 0.
Receive Control Data Ready
0: Indicates that the SIRCR stores no valid data.
1: Indicates that the SIRCR stores valid data.
•
•
•
•
FIFO does not exceed the size specified by the
TFWM bit in SIFCTR.
FIFO exceeds the size specified by the TFWM bit in
SIFCTR.
This bit is valid when the TXE bit in SICTR is 1.
This bit indicates a state; if the size of empty space
in the transmit FIFO is less than the size specified
by the TFWM bit in SIFCTR, the SIOF clears this
bit.
If the issue of interrupts by this bit is enabled, an
SIOF interrupt is issued.
If SIRCR is written when this bit is set to 1, SIRCR
is modified by the latest data.
This bit is valid when the RXE bit in SICTR is set to
1.
This bit indicates a state of the SIOF. If SIRCR is
read, the SIOF clears this bit.
If the issue of interrupts by this bit is enabled, an
SIOF interrupt is issued.