R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1175

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

In serial reception, the SCIF operates as described below.
1. The SCIF monitors the transmission line, and if a 0-start bit is detected, performs internal
2. The received data is stored in SCRSR in LSB-to-MSB order.
3. The parity bit and stop bit are received.
4. If the RIE bit in SCSCR is set to 1 when the RDF or DR flag changes to 1, a receive-FIFO-
Figure 27.13 shows an example of the operation for reception in asynchronous mode.
synchronization and starts reception.
After receiving these bits, the SCIF carries out the following checks.
(a) Stop bit check: The SCIF checks whether the stop bit is 1. If there are two stop bits, only
(b) The SCIF checks whether receive data can be transferred from SCRSR to SCFRDR.*
(c) Overrun error check: The SCIF checks that the ORER flag is 0, indicating that no overrun
(d) Break check: The SCIF checks that the BRK flag is 0, indicating that the break state is not
data-full interrupt (RXI) request is generated.
If the RIE bit or REIE bit in SCSCR is set to 1 when the ER flag changes to 1, a receive-error
interrupt (ERI) request is generated.
If the RIE bit or REIE bit in SCSCR is set to 1 when the BRK or ORER flag changes to 1, a
break reception interrupt (BRI) request is generated.
Note: * Reception continues even when a parity error or framing error occurs.
RDF
FER
the first is checked.
error has occurred.*
set.*
If (b), (c), and (d) checks are passed, the receive data is stored in SCFRDR.
Serial
data
1
Start
bit
0
(Example with 8-Bit Data, Parity, One Stop Bit)
Figure 27.13 Sample SCIF Receive Operation
D0
One frame
D1
Data
D7
RXI interrupt
request
Parity
bit
0/1
Section 27 Serial Communication Interface with FIFO (SCIF)
Stop
bit
1
Start
bit
0
Data read and RDF flag
read as 1 then cleared to
0 by RXI interrupt handler
D0
Rev. 2.00 May 22, 2009 Page 1105 of 1982
D1
Data
D7
Parity
bit
0/1
Stop
bit
ERI interrupt request
generated by receive
error
0
REJ09B0256-0200
0/1