R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1282

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 29 Serial I/O with FIFO (SIOF)
Rev. 2.00 May 22, 2009 Page 1212 of 1982
REJ09B0256-0200
Bit
10
9
8
7, 6
5
4
3
2
1
0
Bit Name
RCRDYE
RFFULE
RDREQE
—
SAERRE
FSERRE
TFOVFE
TFUDFE
RFUDFE
RFOVFE
Initial
Value
0
0
0
All 0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
Receive FIFO Full Enable
Transmit FIFO Overflow Enable
Receive FIFO Overflow Enable
Description
Receive Control Data Ready Enable
0: Disables interrupts due to receive control data ready
1: Enables interrupts due to receive control data ready
0: Disables interrupts due to receive FIFO full
1: Enables interrupts due to receive FIFO full
Receive Data Transfer Request Enable
0: Disables interrupts due to receive data transfer
1: Enables interrupts due to receive data transfer
Reserved
These bits are always read as 0. The write value should
always be 0.
Slot Assign Error Enable
0: Disables interrupts due to slot assign error
1: Enables interrupts due to slot assign error
Frame Synchronization Error Enable
0: Disables interrupts due to frame synchronization
1: Enables interrupts due to frame synchronization error
0: Disables interrupts due to transmit FIFO overflow
1: Enables interrupts due to transmit FIFO overflow
Transmit FIFO Underflow Enable
0: Disables interrupts due to transmit FIFO underflow
1: Enables interrupts due to transmit FIFO underflow
Receive FIFO Underflow Enable
0: Disables interrupts due to receive FIFO underflow
1: Enables interrupts due to receive FIFO underflow
0: Disables interrupts due to receive FIFO overflow
1: Enables interrupts due to receive FIFO overflow
error
requests
requests