R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 677

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Table 14.11 DMA Transfer Matrix in On-Chip Peripheral module Request Mode
[Legend]
Yes:
No:
Note:
(4)
When the priority is set in fixed mode (CH0 > CH1) and channel 1 is transferring in burst mode, if
there is a transfer request to channel 0 with a higher priority, the transfer of channel 0 will begin
immediately.
At this time, if channel 0 is also operating in burst mode, the channel 1 transfer will continue after
the channel 0 transfer has completely finished.
When channel 0 is in cycle steal mode, channel 0 with a higher priority performs the transfer of
one transfer unit and the channel 1 transfer is continuously performed without releasing the bus
mastership. The bus mastership will then switch between the two in the order channel 0, channel
1, channel 0, and channel 1.
This example is shown in figure 14.9. When multiple channels are operating in burst modes, the
channel with the highest priority is executed first.
When DMA transfer is executed in the multiple channels, the bus mastership will not be given to
the bus master until all competing burst transfers are complete.
Transfer Source
LBSC space
DDRIF space
PCIC space
On-chip peripheral
module*
L RAM
Bus Mode and Channel Priority
Transfer is available.
Transfer is not available.
1. When the transfer source or the destination is an on-chip peripheral module, the
1
transfer size should be the same value of its register access size.
The transfer source or the transfer destination should be a register of request source in
on-chip peripheral module request mode. This transfer is available only cycle steal
mode, and when the transfer request source is an on-chip peripheral module, the
transfer is available in channel 0 to 5.
LBSC space DDRIF space PCIC space
No
No
No
Yes
No
No
No
No
Yes
No
Section 14 Direct Memory Access Controller (DMAC)
Transfer Destination
No
No
No
Yes
No
Rev. 2.00 May 22, 2009 Page 607 of 1982
On-chip
peripheral
module*
Yes
Yes
Yes
Yes
Yes
1
REJ09B0256-0200
L RAM
No
No
No
Yes
No