R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 663

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

14.4
When there is a DMA transfer request, the DMAC starts the transfer according to the
predetermined channel priority; when the transfer end conditions are satisfied, it ends the transfer.
Transfers can be requested in three modes: auto request, external request, and on-chip peripheral
module request. In bus mode, burst mode or cycle steal mode can be selected.
14.4.1
DMA transfer requests are basically generated in either the data transfer source or destination, but
they can also be generated by external devices or on-chip peripheral modules that are neither the
source nor the destination. Transfers can be requested in three modes: auto request, external
request, and on-chip peripheral module request. The request mode is selected in the bits RS[3:0] in
CHCR0 to CHCR5, and DMARS0 to DMARS2.
(1)
When there is no transfer request signal from an external source, as in a memory-to-memory
transfer or a transfer between memory and an on-chip peripheral module unable to request a
transfer, auto-request mode allows the DMAC to automatically generate a transfer request signal
internally. When the DE bits in CHCR0 to CHCR5 and the DME bit in DMAOR are set to 1, the
transfer begins so long as the AE and NMIF bits in DMAOR are all 0.
(2)
In this mode, a transfer is performed at the request signal (DREQ0 to DREQ3) of an external
device. This mode is valid only in channel 0 to 3. In this mode, the RS[3:0] bits in CHCRn (n = 0
to 3) should be B'0000. When this mode is selected, if the DMA transfer is enabled (DE = 1, DME
= 1, TE = 0, AE = 0, NMIF = 0), a transfer is performed upon a request at the DREQ input.
Table 14.5 Setting External Request Mode with RS bit
Choose to detect DREQ by either the edge or level of the signal input with the DL bit and DS bit
in CHCRn (n = 0 to 3) as shown in table 14.6. The source of the transfer request does not have to
be the data transfer source or destination.
RS[3] RS[2] RS[1] RS[0] Address Mode
0
Auto-Request Mode
External Request Mode
0
Operation
DMA Transfer Requests
CHCR
0
0
Dual Address Mode
Section 14 Direct Memory Access Controller (DMAC)
Transfer Source
Any
Rev. 2.00 May 22, 2009 Page 593 of 1982
Transfer Destination
Any
REJ09B0256-0200