R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1104

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 26 I
Rev. 2.00 May 22, 2009 Page 1034 of 1982
REJ09B0256-0200
Bit
4
3
2
1
2
C Bus Interface (IIC)
Bit Name
SSR
SDE
SDT
SDR
Initial Value
0
0
0
0
R/W
R/W*
R/W*
R/W*
R/W*
Description
Slave Stop Received
A stop condition has been output on the bus.
This status bit becomes active after the rising
edge of SDA during the stop bit.
Slave Data Empty
Indicates that data to be transmitted has been
loaded into the shift register. At the start of
byte data transmission, the contents of the
ICTXD register are loaded into a shift register
ready for outputting data on the bus. This
status bit indicates that data has been loaded
and the ICTXD register is again ready for
further data. This status bit becomes active on
the falling edge of SCL before the first data bit.
During the single-buffer mode, this bit must be
reset every time new data has been written to
the ICTXD register. This is because the slave
holds SCL low to stop the bus while this bit is
set to 1 even if a slave transmission cycle is
started.
Slave Data Transmitted
A byte of data has been transmitted to the bus.
This bit becomes active after the falling edge
of SCL during the last data bit.
Slave Data Received
A byte of data has been received from the bus
and is ready for read in the receive data
register. This bit becomes active after the
falling edge of SCL during the last data bit.
During the single-buffer mode, this bit must be
reset after data has been read from the ICRXD
register.
When SDBS is set to 1, SCL will be held low
from the timing when the receive data register
acquires the data packet until the SDR flag is
cleared.