R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 731
R5S77631Y266BGV
Manufacturer Part Number
R5S77631Y266BGV
Description
IC SUPERH MPU ROMLESS 499BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R5S77631Y266BGV.pdf
(2056 pages)
Specifications of R5S77631Y266BGV
Core Processor
SH-4A
Core Size
32-Bit
Speed
266MHz
Connectivity
Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
107
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
499-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5S77631Y266BGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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17.5
17.5.1
A power-on reset is to initialize the on-chip PLL circuit when this LSI goes to the power-on reset
state by the PRESET pin low level input and then it is necessary to ensure the synchronization
settling time of the PLL circuit. Therefore, do not input high level to the PRESET pin during the
PLL synchronization settling time. The PLL synchronization settling time is the total value of the
PLL1 synchronization settling time and the PLL2 synchronization settling time.
After the PRESET pin input level is changed from low level to high level, the reset state is
continued during the reset holding time in the LSI. The reset holding time is 20 clock cycles of the
EXTAL pin input clock and thereafter equal to or more than 45 clock cycles of the peripheral
clock (Pck0).
The STATUS [1:0] pins output timing that indicates the reset state is asynchronous, and that
indicates a normal operation is synchronous with the peripheral clock (Pck0) and asynchronous
with both the EXTAL pin input clock and the CLKOUT pin input clock.
(1)
When turning on power supply, the PRESET pin input level should be low level. And the TRST
pin input level should be low level to initialize the H-UDI.
Turning On Power Supply
Status Pin Change Timing during Reset
Power-On Reset by PRESET
Section 17 Watchdog Timer and Reset (WDT)
Rev. 2.00 May 22, 2009 Page 661 of 1982
REJ09B0256-0200
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