R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 180

IC SUPERH MPU ROMLESS 499BGA

R5S77631Y266BGV

Manufacturer Part Number
R5S77631Y266BGV
Description
IC SUPERH MPU ROMLESS 499BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R5S77631Y266BGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
266MHz
Connectivity
Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
107
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
499-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5S77631Y266BGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 5 Exception Handling
5.4
Table 5.3 shows the types of exceptions, with their relative priorities, vector addresses, and
exception/interrupt codes.
Table 5.3
Rev. 2.00 May 22, 2009 Page 110 of 1982
REJ09B0256-0200
Exception
Category
Reset
General
exception
Exception Types and Priorities
Execution
Mode
Abort type
Re-
execution
type
Exceptions
Exception
Power-on reset
Manual reset
H-UDI reset
Instruction TLB multiple-hit
exception
Data TLB multiple-hit exception 1
User break before instruction
execution*
Instruction address error
Instruction TLB miss exception
Instruction TLB protection
violation exception
General illegal instruction
exception
Slot illegal instruction exception 2
General FPU disable exception 2
Slot FPU disable exception
Data address error (read)
Data address error (write)
Data TLB miss exception (read) 2
Data TLB miss exception (write) 2
Data TLB protection
violation exception (read)
Data TLB protection
violation exception (write)
FPU exception
Initial page write exception
1
Priority
Level*
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
Priority
Order*
1
2
1
3
4
0
1
2
3
4
4
4
4
5
5
6
6
7
7
8
9
2
Vector
Address
H'A000 0000 —
H'A000 0000 —
H'A000 0000 —
H'A000 0000 —
H'A000 0000 —
(VBR/DBR)
(VBR)
(VBR)
(VBR)
(VBR)
(VBR)
(VBR)
(VBR)
(VBR)
(VBR)
(VBR)
(VBR)
(VBR)
(VBR)
(VBR)
(VBR)
Exception Transition
Direction*
H'100/— H'1E0
H'400
H'100
H'100
H'100
H'100
H'400
H'100
Offset
H'100
H'100
H'100
H'100
H'400
H'100
H'100
H'100
3
H'020
H'140
H'040
H'1A0
H'0E0
H'100
H'040
H'060
H'080
Exception
Code*
H'000
H'000
H'140
H'0E0
H'0A0
H'180
H'800
H'820
H'0A0
H'0C0
H'120
4

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