R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1405

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

(5)
Flash memory operation commands include a number of commands involving read data. Such
commands confirm the card status through the command argument and command response, and
receive card information and flash memory data from the MMC_DAT pin.
In multiblock transfer, there are two methods of transfer: the open-ended and pre-defined methods.
The open-ended method suspends operation at each block transfer and waits for an instruction as
to whether to continue the command sequence. The pre-defined method starts transferring with the
block number set beforehand.
When the FIFO is full between blocks in multiblock transfer, the command sequence is
suspended. Once the command sequence is suspended, any necessary processing of the data in
FIFO must be done before the command sequence is continued.
Figures 31.7 to 31.9 show examples of the command sequence for commands with read data.
Figures 31.10 to 31.12 show the operational flows for commands with read data.
• Create settings to issue the command, and clear FIFO.
• Set the START bit in CMDSTRT to 1 to start command transmission.
• Command transmission completion can be confirmed through the command transmit end
• The command response is received from the card.
• If the card returns no command response, the command response is detected through the
• Read data is received from the card.
• The inter-block suspension in multiblock transfer and suspension due to FIFO full are detected
• The end of the command sequence is detected by poling the BUSY flag in CSTR or the data
interrupt (CMDI).
command timeout error (CTERI).
through the data transfer end interrupt (DTI) and FIFO full interrupt (FFI), respectively.
To continue the command sequence, the RD_CONTI bit in OPCR should be set to 1. To end
the command sequence, the CMDOFF bit in OPCR should be set to 1, and CMD12 should be
issued. Unless the sequence is suspended in a pre-defined multiblock transfer, CMD12 is not
needed.
transfer end interrupt (DTI).
Commands with Read Data
Section 31 Multimedia Card Interface (MMCIF)
Rev. 2.00 May 22, 2009 Page 1335 of 1982
REJ09B0256-0200