R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 639

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

14.2
The external pins for the DMAC are described below. Table 14.1 lists the configuration of the pins
that are connected to external device. The DMAC has pins for four channels (channel 0 to 3) for
external bus use.
The input/output pins of channel 1 are divided in two groups: normal I/O group and mirror I/O
group. The input/output operations of pins in two groups are always the same. The pin select
register of the GPIO is used to select the Channel 1 pins.
Table 14.1 Pin Configuration
Channel
0
1
Normal
I/O
Pins
Miller
I/O
Pins
Input/Output Pins
Pin Name Function
DREQ0*
DACK0*
TEND0*
DREQ1*
DACK1*
TEND1*
DREQ1M*
DACK1M*
TEND1M*
2
2
2
2
1
1
2
2
1
DMA transfer request
DMA transfer request
acknowledge
DMA transfer end
notification
DMA transfer request
DMA transfer request
acknowledge
DMA transfer end
notification
DMA transfer request
DMA transfer request
acknowledge
DMA transfer end
notification
I/O
Input
Output Strobe output from channel 0 to
Output DMA transfer end output from channel
Input
Output Strobe output from channel 1 to
Output DMA transfer end output from channel
Input
Output Strobe output from channel 1 to
Output DMA transfer end output from channel
Section 14 Direct Memory Access Controller (DMAC)
Description
DMA transfer request input from
external device to channel 0
external device which has output,
regarding DMA transfer request
0 to external device
DMA transfer request input from
external device to channel 1
external device which has output,
regarding DMA transfer request
1 to external device
DMA transfer request input from
external device to channel 1
external device which has output,
regarding DMA transfer request
1 to external device
Rev. 2.00 May 22, 2009 Page 569 of 1982
REJ09B0256-0200