R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1824

IC SUPERH MPU ROMLESS 499BGA

R5S77631Y266BGV

Manufacturer Part Number
R5S77631Y266BGV
Description
IC SUPERH MPU ROMLESS 499BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R5S77631Y266BGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
266MHz
Connectivity
Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
107
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
499-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5S77631Y266BGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 40 General Purpose I/O (GPIO)
40.2.42 Pin Select Register 3 (PSEL3)
PSEL3 is a 16-bit readable/writable register that selects the functions of the Port L (PTL), and Port
M (PTM) pins multiplexed with “other function”.
When using the pins with “other function” assigned, set PSEL3 and then set the corresponding
port control register to select “other function”.
Rev. 2.00 May 22, 2009 Page 1754 of 1982
REJ09B0256-0200
Initial value:
Bit
15
14 to 12 PTSEL3
11
R/W:
Bit:
Bit Name
[14:12]
15
R
0
R/W
14
1
PTSEL3[14:12]
R/W
13
0
Initial
value
0
100
0
R/W
12
0
11
R
0
R/W
R
R/W
R
R/W
10
1
PTSEL3[10:8]
Description
Reserved
This bit is always read as 0, and the write value should
always be 0.
These bits select the functions of Port L (PTL7 to PTL4)
and Port M (PTM7 to PTM1).
[Legend]
x: Don't care
Notes: 1. When 32-bit is selected as the data bus
Reserved
This bit is always read as 0, and the write value should
always be 0.
R/W
9
0
Bit setting
PTSEL3[14:12] PTL7 to PTL4
1
000
001
010
011
xx
R/W
8
0
2. When clearing interrupt mask of the
width in the LBSC, select this pin function.
interrupt controller (INTC) with the PCIC
function selected, make sure to select the
PCIC function with this register in advance.
R
7
0
R/W
6
1
LBSC*
EXCPU
LCDC
MII0
DMAC1
STIF0
PTSEL3[6:4]
R/W
5
0
1
/
Selected function
R/W
4
0
PCIC
R
*
3
0
2
R/W
2
1
PTM7 to
PTM1
LBSC*
EXCPU
RMII0
MII0
RMII0
STIF0
PTSEL3[2:0]
R/W
1
0
1
/
R/W
0
0

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