R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 433

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

As regards the number of bus cycles, 0 to 25 wait cycles inserted by CS1WCR can be selected.
When the burst ROM interface is used, a burst pitch number in the range of 0 to 7 is selectable
with bits BW[2:0] in CS1BCR.
Any number of wait cycles can be inserted in each bus cycle through the external wait pin (RDY).
(When the insert number is 0, the RDY signal is ignored.)
The setup time and hold time (cycle number) of the address and CS1 signals to the read and write
strobe signals can be set within a range of 0 to 7 cycles by CS1WCR. The BS hold cycles can be
set within a range of 0 to 1 when the number of read and write strobe setup wait is 1 or more.
(3)
For area 2, external address bits A28 to A26 are 010.
The interfaces that can be set for this area are the SRAM, MPX, burst ROM and DDR-SDRAM
interfaces.
When the SRAM interface is used, a bus width of 8, 16, or 32 bits is selectable with bits SZ[1:0]
in CS2BCR. When the MPX interface is used, a bus width of 32 bits should be selected through
bits SZ[1:0] in CS2BCR.
When area 2 is accessed, the CS2 signal is asserted (except for DDR-SDRAM area). In the case
where the SRAM interface is set, the RD signal, which can be used as OE, and write control
signals WE0 to WE3 are asserted.
As regards the number of bus cycles, 0 to 25 wait cycles inserted by CS2WCR can be selected.
Any number of wait cycles can be inserted in each bus cycle through the external wait pin (RDY).
(When the insert number is 0, the RDY signal is ignored.)
The setup time and hold time (cycle number) of the address and CS2 signals to the read and write
strobe signals can be set within a range of 0 to 7 cycles by CS2WCR. The BS hold cycles can be
set within a range of 0 to 1 when the number of read and write strobe setup wait is 1 or more.
When the DDR-SDRAM is used, see section 12, DDR-SDRAM Interface (DDRIF).
(4)
For area 3, external address bits A28 to A26 are 011.
This area is used only for the DDR-SDRAM interface.
Area 2
Area 3
Section 11 Local Bus State Controller (LBSC)
Rev. 2.00 May 22, 2009 Page 363 of 1982
REJ09B0256-0200