R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 142

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 3 Instruction Set
Table 3.8
Table 3.9
Rev. 2.00 May 22, 2009 Page 72 of 1982
REJ09B0256-0200
Instruction
BF
BF/S
BT
BT/S
BRA
BRAF
BSR
BSRF
JMP
JSR
RTS
Instruction
CLRMAC
CLRS
CLRT
ICBI
LDC
LDC
LDC
@Rn
Rm,SR
Rm,GBR Rm → GBR
Rm,VBR Rm → VBR
label
label
label
label
label
Rn
label
Rn
@Rn
@Rn
Branch Instructions
System Control Instructions
Operation
0 → MACH, MACL
0 → S
0 → T
Invalidates instruction cache
block indicated by virtual
address
Rm → SR
Operation
When T = 0, disp × 2 + PC +
4 → PC
When T = 1, nop
Delayed branch; when T = 0,
disp × 2 + PC + 4 → PC
When T = 1, nop
When T = 1, disp × 2 + PC +
4 → PC
When T = 0, nop
Delayed branch; when T = 1,
disp × 2 + PC + 4 → PC
When T = 0, nop
Delayed branch, disp × 2 +
PC + 4 → PC
Delayed branch, Rn + PC + 4 →
PC
Delayed branch, PC + 4 → PR,
disp × 2 + PC + 4 → PC
Delayed branch, PC + 4 → PR,
Rn + PC + 4 → PC
Delayed branch, Rn → PC
Delayed branch, PC + 4 → PR,
Rn → PC
Delayed branch, PR → PC
Instruction Code
10001011dddddddd —
10001111dddddddd —
10001001dddddddd —
10001101dddddddd —
1010dddddddddddd —
0000nnnn00100011 —
1011dddddddddddd —
0000nnnn00000011 —
0100nnnn00101011 —
0100nnnn00001011 —
0000000000001011 —
Instruction Code
0000000000101000 —
0000000001001000 —
0000000000001000 —
0000nnnn11100011 
0100mmmm00001110 Privileged
0100mmmm00011110 —
0100mmmm00101110 Privileged
Privileged
Privileged T Bit
—
—
—
0

LSB
—
T Bit
—
—
—
—
—
—
—
—
—
—
—
New
—
—
—
New
—
—
—
New
—
—
—
—
—
—
—
—
—
—
—