R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 18

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

13.5 Usage Notes ....................................................................................................................... 564
Section 14 Direct Memory Access Controller (DMAC)................................... 567
14.1 Features.............................................................................................................................. 567
14.2 Input/Output Pins............................................................................................................... 569
14.3 Register Descriptions......................................................................................................... 571
14.4 Operation ........................................................................................................................... 593
14.5 Usage Notes ....................................................................................................................... 616
Section 15 External CPU Interface (EXCPU)................................................... 623
15.1 Features.............................................................................................................................. 623
15.2 Input/Output Pins............................................................................................................... 624
Rev. 2.00 May 22, 2009 Page xvi of lxviii
13.4.7 Power Management .............................................................................................. 551
13.4.8 PCI Local Bus Basic Interface.............................................................................. 552
13.5.1 Notes on PCIC Target Reading............................................................................. 564
13.5.2 Notes on Host Mode ............................................................................................. 564
14.3.1 DMA Source Address Registers (SAR0 to SAR5) ............................................... 574
14.3.2 DMA Source Address Registers (SARB0 to SARB3).......................................... 575
14.3.3 DMA Destination Address Registers (DAR0 to DAR5) ...................................... 575
14.3.4 DMA Destination Address Registers (DARB0 to DARB3) ................................. 576
14.3.5 DMA Transfer Count Registers (TCR0 to TCR5)................................................ 576
14.3.6 DMA Transfer Count Registers (TCRB0 to TCRB3)........................................... 577
14.3.7 DMA Channel Control Registers (CHCR0 to CHCR5) ....................................... 578
14.3.8 DMA Operation Register (DMAOR) ................................................................... 586
14.3.9 DMA Extended Resource Selectors (DMARS0 to DMARS2)............................. 589
14.4.1 DMA Transfer Requests ....................................................................................... 593
14.4.2 Channel Priority.................................................................................................... 597
14.4.3 DMA Transfer Types............................................................................................ 600
14.4.4 DMA Transfer Flow ............................................................................................. 608
14.4.5 Repeat Mode Transfer .......................................................................................... 610
14.4.6 Reload Mode Transfer .......................................................................................... 611
14.4.7 DREQ Pin Sampling Timing ................................................................................ 612
14.5.1 Module Stop ......................................................................................................... 616
14.5.2 Address Error........................................................................................................ 616
14.5.3 Notes on Burst Mode Transfer.............................................................................. 616
14.5.4 DACK and TEND Output Divisions .................................................................... 617
14.5.5 CS Output Settings and Transfer Size Larger than External Bus Width............... 617
14.5.6 DACK and TEND Assertion and DREQ Sampling.............................................. 617
14.5.7 DMA Transfer to DMAC Prohibited.................................................................... 621
14.5.8 NMI Interrupt........................................................................................................ 621