R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1668

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 37 LCD Controller (LCDC)
37.3.3
LDDFR sets the bit alignment for pixel data in one byte and selects the data type and number of
colors used for display so as to match the display driver software specifications.
Rev. 2.00 May 22, 2009 Page 1598 of 1982
REJ09B0256-0200
Initial value:
Bit
15 to 9 
8
7
R/W:
Bit:
Bit Name
PABD

LCDC Data Format Register (LDDFR)
15

R
0
14

R
0
Initial Value
All 0
0
0
13

R
0
12

R
0
11

R
0
R/W
R
R/W
R
10

R
0

R
9
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Byte Data Pixel Alignment
Sets the pixel data alignment type in one byte of
data. The contents of aligned data per pixel are the
same regardless of this bit's setting. For example,
data H'05 should be expressed as B'0101 which is
the normal style handled by a MOV instruction of the
this CPU, and should not be selected between
B'0101 and B'1010.
0: Big endian for byte data
1: Little endian for byte data
Reserved
This bit is always read as 0. The write value should
always be 0.
PABD
R/W
8
0

R
7
0
R/W
6
0
R/W
5
0
R/W
4
0
DSPCOLOR[6:0]
R/W
3
1
R/W
2
1
R/W
1
0
R/W
0
0