R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1610

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 36 USB Function Controller (USBF)
36.3.29 FIFO Clear Register 0 (FCLR0)
FCLR is a one shot register to clear the FIFO buffers for endpoints 0 to 3. Writing 1 to a bit clears
the data in the corresponding FIFO buffer.
In case of reception FIFO, by writing data in the FIFO buffer, the data by which PKTE in TRG is
not written to 1 and the data enabled by writing 1 can be cleared. In case of OUT FIFO, the data of
which reception has not been completed can be cleared.
Both sides of the dual-configuration FIFO buffers (EP1 or EP3) can be cleared.
The corresponding interrupt flag is not cleared by this clear instruction. Do not clear a FIFO buffer
during transmission and reception.
Rev. 2.00 May 22, 2009 Page 1540 of 1982
REJ09B0256-0200
Bit
31 to 8 
7
6
5
4
3, 2
1
0
Initial value:
Initial value:
R/W:
R/W:
Bit: 31
Bit: 15
Bit Name

EP3 CLR
EP1 CLR
EP2 CLR

EP0o CLR
EP0i CLR
—
—
—
—
R
R
30
—
14
—
—
—
R
R
29
—
13
—
—
—
R
R
Initial Value R/W Description
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
28
—
12
—
—
—
R
R
27
—
11
—
—
—
R
R
26
—
10
—
—
—
R
R
R
W
W
W
W
W
W
W
25
—
—
—
—
R
R
9
Reserved
The write value should always be 0.
Reserved
The write value should always be 0.
EP0o Clear
EP0i Clear
Reserved
These bits are always read as undefined value.
Write value should always be 0.
EP3 Clear
EP1 Clear
EP2 Clear
24
—
—
—
—
R
R
8
23
—
—
—
—
W
R
7
CLR
EP3
22
—
—
—
W
R
6
CLR
EP1
21
—
—
—
W
R
5
CLR
EP2
20
—
—
—
W
R
4
19
—
—
—
—
W
R
3
18
—
—
—
—
W
R
2
EP0o
CLR
17
—
—
—
W
R
1
EP0i
CLR
16
—
—
—
W
R
0