R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1269

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
9
8
Bit Name
TXE
RXE
Initial
Value
0
0
R/W
R/W
R/W
Description
Transmit Enable
0: Disables data transmission from the SIOF_TXD pin
1: Enables data transmission from the SIOF_TXD pin
•
•
This bit is initialized upon a transmit reset.
Receive Enable
0: Disables data reception from SIOF_RXD
1: Enables data reception from SIOF_RXD
•
•
This bit is initialized upon receive reset.
This bit setting becomes valid at the start of the next
frame (at the rising edge of the SIOF_SYNC signal).
When the 1 setting for this bit becomes valid, the
SIOF issues a transmit transfer request according
to the setting of the TFWM bit in SIFCTR. When
transmit data is stored in the transmit FIFO,
transmission of data from the SIOF_TXD pin
begins.
This bit setting becomes valid at the start of the next
frame (at the rising edge of the SIOF_SYNC signal).
When the 1 setting for this bit becomes valid, the
SIOF begins the reception of data from the
SIOF_RXD pin. When receive data is stored in the
receive FIFO, the SIOF issues a reception transfer
request according to the setting of the RFWM bit in
SIFCTR.
Rev. 2.00 May 22, 2009 Page 1199 of 1982
Section 29 Serial I/O with FIFO (SIOF)
REJ09B0256-0200